How to use the can bus bit timing calculator
- Choose Check my settings to test a setting, or Find settings to search for one.
- Enter the controller clock in megahertz and the bit rate in kilobits per second.
- To check, enter the prescaler (BRP), TSEG1 and TSEG2. To search, enter a target sample point and your controller's limits.
- Read the sample point, the number of time quanta per bit, the actual bit rate and its error, or the table of exact settings.
Formula
Time quantum tq = BRP / clock
Time quanta per bit = 1 (sync) + TSEG1 + TSEG2
Bit rate = clock / (BRP x time quanta per bit)
Sample point = (1 + TSEG1) / time quanta per bit
The sample point is where in the bit the controller reads the bus level. TSEG1 holds the propagation segment and the first phase segment, and TSEG2 holds the second phase segment.
8 MHz clock and 500 kbit/s
With a prescaler of 1, TSEG1 of 13 and TSEG2 of 2, one bit has 1 + 13 + 2 = 16 time quanta. Each time quantum is 125 ns, so a bit lasts 2 microseconds and the bit rate is exactly 500 kbit/s, with an error of 0.000 percent. The sample point is (1 + 13) / 16 = 87.5 percent.
Searching a 16 MHz clock for 250 kbit/s with a target of 87.5 percent lists the exact settings, with the closest first at 87.50 percent. An 80 MHz clock at 1 Mbit/s with a target of 80 percent has exact settings with prescalers of 4, 5, 8 and 10, with 20, 16, 10 and 8 time quanta per bit.
Choosing the sample point
A later sample point gives the signal more time to settle, which helps on long buses, and an earlier one leaves more room for resynchronization. Protocol standards and application guides recommend sample points for different bit rates and bus lengths, and the target of 87.5 percent on the page is only an example. Use the figure that your standard or your system design asks for.
To convert register values between number bases, use the binary calculator. To find the step size of an analog to digital converter in the same system, use the ADC resolution calculator.
Limits of the controller
Every controller has limits on the prescaler, the segment lengths and the time quanta per bit. The defaults on the page (64, 16 and 8, and 8 to 25 quanta) fit many classic controllers, and you can change them to match yours. Some controllers store a segment as its value minus one, so check how your data sheet writes the registers.
The page does not check the synchronization jump width, the oscillator tolerance or the propagation delay of the cable and transceivers. Those depend on your network, and a design check should cover them. For the data in flight on a link, see the bandwidth delay product calculator.
Assumptions and limits
- The classic CAN bit timing model: one sync segment, then TSEG1 and TSEG2 in time quanta.
- Only settings that give the bit rate exactly are listed in the search.
- Limits on prescaler and segments are the ones you enter. The defaults are examples.
- Oscillator tolerance, bus length and transceiver delay are not checked.
Frequently asked questions
What is the sample point in CAN?
It is the point inside a bit, as a percentage of the bit time, at which the controller reads the bus level.
How do I find the bit rate from the settings?
Divide the clock by the prescaler times the time quanta per bit, where time quanta per bit is 1 plus TSEG1 plus TSEG2.
What is a time quantum?
It is the smallest unit of time in the bit timing, equal to the prescaler divided by the clock.
Why do some settings not appear in the search?
Only settings that give the bit rate exactly, with whole time quanta and within your limits, are listed.