Productivity and Utilities

Bit Field Mask Generator

List your fields as name and width, one per line, and pick a register width to get masks and shifts.

Your numbers

One field per line, such as mode 3. Names use letters, digits and underscores. Widths are from 1 to 64 bits.

Result

Bits used

10 of 16

6 bits are left over. Unused bits mask: 0xFC00.

Fields
4
Bits used
10
Bits left
6
Mask of all fields
0x03FF

Fields

FieldBitsShiftMaskLargest value
enable000x00011
mode3:110x000E7
prescale7:440x00F015
irq9:880x03003

C definitions

Line
#define ENABLE_SHIFT 0
#define ENABLE_MASK 0x0001u
#define MODE_SHIFT 1
#define MODE_MASK 0x000Eu
#define PRESCALE_SHIFT 4
#define PRESCALE_MASK 0x00F0u
#define IRQ_SHIFT 8
#define IRQ_MASK 0x0300u

Extract and insert

OperationExpression
Extract a field(reg & NAME_MASK) >> NAME_SHIFT
Insert a valuereg = (reg & ~NAME_MASK) | ((value << NAME_SHIFT) & NAME_MASK)
How this was calculated
  1. Fields are placed in the order listed, starting at bit 0. Each field takes the next free bits above the one before it.
  2. The mask of a field of width w at shift s is ((1 << w) - 1) << s. The shift is the position of its lowest bit.
  3. To read a field, AND the register with its mask and shift right by the shift. To write one, clear its bits with the inverted mask and OR in the shifted value.

Calculated using SumPanda.com · https://sumpanda.com/bit-field-mask-generator/

Results are estimates for general information. Verify important figures before relying on them.

Next step

How to use the bit field mask generator

  1. List your fields, one per line, as a name and a width in bits, such as mode 3.
  2. Choose the register width: 8, 16, 32 or 64 bits.
  3. Choose where the first field sits: at bit 0 (the low end) or at the top bit.
  4. Read the shift and mask of every field, the C definitions and the extract and insert expressions.

Formula

mask = ((1 << width) - 1) << shift

extract a field: (reg & MASK) >> SHIFT

insert a value: reg = (reg & ~MASK) | ((value << SHIFT) & MASK)

the fields must fit: total width <= register width

The shift of a field is the position of its lowest bit. Fields are placed one after another in the order you list them, with no gaps.

A 16 bit control register

Four fields are listed: enable (1 bit), mode (3 bits), prescale (4 bits) and irq (2 bits). Placed from bit 0, enable takes bit 0 with mask 0x0001, mode takes bits 3 to 1 with mask 0x000E, prescale takes bits 7 to 4 with mask 0x00F0, and irq takes bits 9 to 8 with mask 0x0300. That is 10 bits of 16, and the unused bits mask is 0xFC00.

Placed from the top bit instead, enable is bit 15 (0x8000), mode is bits 14 to 12 (0x7000), prescale is bits 11 to 8 (0x0F00) and irq is bits 7 to 6 (0x00C0). A 32 bit flags word with read, write and exec bits, an 8 bit owner and a 16 bit size uses 27 of 32 bits, with the size mask 0x07FFF800.

Why use masks and shifts

Hardware registers, protocol headers and file formats pack several small values into one number. Writing masks by hand invites mistakes, especially for 64 bit values. A table of shift and mask for each field gives you exact constants to paste, and the check that fields do not overlap or overflow the register is automatic.

The constants here are given in C style, but the same masks work in any language that has bit operations. In languages with arbitrary size integers, such as Python, use the mask and shift as written.

Related tools

Try values with the Bitwise Calculator or convert between bases with the Binary Calculator. To see how a register reads in each byte order, use the Byte Order Swap Calculator, and for a familiar bit layout, see the Umask Calculator.

Assumptions and limits

  • Fields are placed in the order listed with no padding between them.
  • Each field is 1 to 64 bits wide, and the total cannot exceed the register width.
  • Names must start with a letter or underscore and use letters, digits and underscores.
  • Reserved or unused bits are left over at the end of the register.
  • The field names and widths shown when the page opens are examples.

Formulas reviewed October 10, 2026. See the calculation methodology for how SumPanda rounds, tests and sources its formulas.

Frequently asked questions

How do I leave a gap between fields?

Add a field for the gap, such as reserved1 2, and ignore its mask. The page keeps it in the layout so later fields land where you expect.

What does 3:1 mean in the Bits column?

It means bits 3 down to 1, three bits wide. A one bit field shows just its bit number.

Why does it complain that the fields do not fit?

The widths add up to more than the register width. Shorten a field, remove one, or choose a wider register.

Can I use the C definitions for 64 bit registers?

Yes. For registers wider than 32 bits the masks are written with the ULL suffix so they stay 64 bit unsigned constants.